Defect Classes - An Overdue Paradigm for CMOS IC
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Using Target Faults To Detect Non-Tartget Defects
Proceedings of the IEEE International Test Conference on Test and Design Validity
"Resistive Shorts" Within CMOS Gates
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Bridging Defects Resistance Measurements in a CMOS Process
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
All Tests for a Fault Are Not Equally Valuable for Defect Detection
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Test Strategy Sensitivity to Defect Parameters
Proceedings of the IEEE International Test Conference
Parametric Bridging Fault Characterization for the Fault Simulation of Library-Based ICs
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Biased Voting: A Method for Simulating CMOS Bridging Faults in the Presence of Variable Gate Logic
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Analyss of Dynamic Effects of Resistive Bridging Faults in CMOS and BiCMOS Digital ICs
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
The concept of resistance interval: a new parametric model for realistic resistive bridging fault
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
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This paper analyzes the different types of test escape with the final objective to propose a solution to minimize some of the test escapes. Using a simple example of short defect in the context of Boolean testing, it is first demonstrated that the defect behavior depends on unpredictable parameters. It is shown that a defect may be detectable with a vector but for a given domain of the unpredictable parameter called the Detection Domain. Using the concept of Detection Domain, 3 different types of test escape are identified. It is then demonstrated that one type of test escape can be minimized using 'Improved fault models'.