Time redundant fault-location in bit-sliced ALU's

Authors:
C. C. Wu
Affiliations:
National Taiwan Institute of Technology, Taipei, Taiwan
Venue:
IEEE Transactions on Computers
Year:
1987

Citing 4
Cited 1

Concurrent Error Detection in ALU's by Recomputing with Shifted Operands

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The STAR (Self-Testing And Repairing) Computer: An Investigation of the Theory and Practice of Fault-Tolerant Computer Design

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Arithmetic Error Codes: Cost and Effectiveness Studies for Application in Digital System Design

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Fault-Tolerant Computing Concepts and Examples

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Reliable Floating-Point Arithmetic Algorithms for Error-Coded Operands

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Abstract

A method of fault location in arithmetic and logic units (ALU's) is proposed. When the failures are confined to adjacent bit slices of the ALU's, the RESO (recomputing with shifted operands) based method can isolate the faulty bit slices by specifying a larger set of ``suspicious'' faulty bit slices, and, therefore, identify the definitely fault-free bit slices in ALU's. The method is applicable to both arithmetic and logic operations.