Cutting the high cost of testing
IEEE Spectrum
Optimal ordering of analog integrated circuit tests to minimize test time
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Analytical fault modeling and static test generation for analog ICs
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Dynamic test signal design for analog ICs
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Fault-based automatic test generator for linear analog circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
CONCERT: a concurrent transient fault simulator for nonlinear analog circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Multifrequency Analysis of Faults in Analog Circuits
IEEE Design & Test
Analog Testing with Time Response Parameters
IEEE Design & Test
Specification-Driven Test Design for Analog Circuits
DFT '98 Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems
LIMSoft: Automated Tool for Design and Test Integration of Analog Circuits
Proceedings of the IEEE International Test Conference on Test and Design Validity
Test Vector Generation for Linear Analog Devices
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Test Generation for Analog Circuits Using Partial Numerical Simulation
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
CLP-based Multifrequency Test Generation for Analog Circuits
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
7.1 Nonlinear Analog DC Fault Simulation by One-Step Relaxation
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
7.2 Enhancing Test Effectiveness for Analog Circuits Using Synthesized Measurements
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Electronic Circuit & System Simulation Methods (SRE)
Electronic Circuit & System Simulation Methods (SRE)
An integrated approach for analog circuit testing with a minimum number of detected parameters
ITC'94 Proceedings of the 1994 international conference on Test
DC_IATP- an iterative analog circuit test generation program for generating DC single pattern tests
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Test generation based diagnosis of device parameters for analog circuits
Proceedings of the conference on Design, automation and test in Europe
Hierarchical ATPG for Analog Circuits and Systems
IEEE Design & Test
Automated System-Level Test Development for Mixed-Signal Circuits
Analog Integrated Circuits and Signal Processing
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Dynamic transient tests can give better parametric and catastrophic fault coverage than both static DC and frequency domain AC tests in minimum test time. However, determination of optimum transient tests is a complex search problem. Previous researchers have used accurate but computationally expensive fault simulation to guide the search for the optimum transient tests. In this paper, we propose to use partial numerical simulation to guide the search for the optimum input test stimulus. The proposed method dynamically adjusts the number of Newton Raphson iterations and transient simulation time steps to perform fast test generation without sacrificing the test quality (fault coverage). This heuristic relies on the observation that although partial numerical circuit simulation may be inaccurate for determining the exact faulty circuit response to an applied test stimulus, it can determine very well how one test stimulus performs relative to another in detecting a fault. Simulation studies show that test generation using partial numerical simulation can generate high quality tests much faster compared to test generation methods based on accurate simulation without compromising test quality.