Specification-Driven Test Design for Analog Circuits

Authors:
Pramodchandran N. Variyam;Abhijit Chatterjee
Affiliations:
-;-
Venue:
DFT '98 Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems
Year:
1998

Citing 0
Cited 4

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Estimating path delay distribution considering coupling noise

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Abstract

In this paper we present a test generation approach for time and frequency domain testing of analog circuits. Tests are generated to detect faulty circuits which violate one or more circuit specifications with- out explicitly performing exhaustive specification based tests. We formulate the test stimulus generation problem as a search problem in which the primary goal is to reduce the probability of classifying a bad circuit as good and vice versa. Genetic algorithms are used to search for the optimum transient and steady state tests.