Testability analysis and multi-frequency ATPG for analog circuits and systems
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Test generation based diagnosis of device parameters for analog circuits
Proceedings of the conference on Design, automation and test in Europe
Hierarchical ATPG for Analog Circuits and Systems
IEEE Design & Test
Analog and Mixed-Signal Benchmark Circuits-First Release
Proceedings of the IEEE International Test Conference
A novel test generation approach for parametric faults in linear analog circuits
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Test Generation for Accurate Prediction of Analog Specifications
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Automated Test Generation and Test Point Selection for Specification Test of Analog Circuits
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
A new ATPG technique (MultiDetect) for testing of analog macros in mixed-signal circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A New ATPG Technique (ExpoTan) for Testing Analog Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper proposes a test generation algorithm combining genetic algorithm for fault diagnosis on linear systems. Most test generation algorithms just used a single value fault model. This test generation algorithm is based on a continuous fault model. This algorithm can improve the treatment of the tolerance problem, including the tolerances of both normal and fault parameters, and enhance the fault coverage rate. The genetic algorithm can be used to choose the characteristic values. The genetic algorithm can enhance precision of test generation algorithm especially for complex fitness functions derived from complex systems under test. The genetic algorithm can also further improve the fault coverage rate by reducing the loop number of divisions of the initial fault range. The experiments are carried out to show this test generation algorithm with a linear system and an integrated circuit.