Analytical fault modeling and static test generation for analog ICs
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Design based analog testing by Characteristic Observation Inference
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Fault-based automatic test generator for linear analog circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
LIMSoft: Automated Tool for Design and Test Integration of Analog Circuits
Proceedings of the IEEE International Test Conference on Test and Design Validity
Test Vector Generation for Linear Analog Devices
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Feedback Driven Backtrace of Analog Signals and its Application to Circuit Verification and Test
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
Test generation for mixed-signal devices using signal flow graphs
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Implicit functional testing for analog circuits
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Automated test pattern generation for analog integrated circuits
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers
Test generation based diagnosis of device parameters for analog circuits
Proceedings of the conference on Design, automation and test in Europe
Hierarchical ATPG for Analog Circuits and Systems
IEEE Design & Test
A Path Sensitization Technique for Testing of Switched Capacitor Circuits
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
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In this paper, we propose an efficient test generation scheme for analog circuits consisting of embedded modules. The proposed scheme simplifies the test generation effort by incrementally generating tests for the individual embedded modules rather than for the full circuit. At each step of the test generation process, the test waveform is incrementally optimized. As input nodes to an embedded module are not directly accessible, the test optimization considers only those waveforms that can be justified from an embedded module input to a primary input of the circuit-under-test using a signal backtrace procedure. The "best" selected test is then evaluated at the full circuit level for controllability of the test stimulus and observability of the test results. In this manner, repeated evaluation of the full circuit over the search space of all test stimuli is not necessary and the complexity of test search can be reduced.