Analytical fault modeling and static test generation for analog ICs
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Testing of analog systems using behavioral models and optimal experimental design techniques
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Dynamic test signal design for analog ICs
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Fault Simulation for Analog Circuits Under Parameter Variations
Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999
Systematic design of a 200 MS/s 8-bit interpolating/averaging A/D converter
Proceedings of the 39th annual Design Automation Conference
Feedback Driven Backtrace of Analog Signals and its Application to Circuit Verification and Test
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
Hierarchical Test Generation for Analog Circuits Using Incremental Test Development
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Speed-up of High Accurate Analog Test Stimulus Optimization
ITC '99 Proceedings of the 1999 IEEE International Test Conference
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An algorithm for the generation of tests for analog integrated circuits is proposed. It starts from a generated fault list and ranges specified by the user and determines optimal test signals that maximize the detectability of all faults. As statistical fluctuations have to be considered when evaluating analog circuits, it is based on a statistical test criterion. Two examples demonstrate the practical use and versatility of this approach.