Nonscan design-for-testability techniques using RT-level design information

• Authors: S. Dey;M. Potkonjak
• Venue: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
• Year: 2006

This paper presents nonscan design-for-testability (DFT) techniques applicable to register-transfer (RT)-level data path circuits. Knowledge of high-level design information, in the form of the RT-level structure, as well as the functions of the RT-level components is utilized to develop effective nonscan DFT techniques. Instead of conventional techniques of selecting flip-flops (FF's) to make systems controllable/observable, execution units (EXU's) are selected using the EXU S-graph introduced in this paper. Controllability/observability points can be implemented using register files and constants. We introduce the notion of k-level controllable and observable loops and demonstrate that it suffices to make all the loops k-level controllable/observable, k>0, to achieve very high test efficiency. The new testability measure eliminates the need by traditional DFT techniques to make all loops directly (zero-level) controllable/observable, reducing significantly the hardware overhead required and making the nonscan DFT approach feasible and effective. We discuss ways of avoiding the formation of reconvergent regions while adding test points to make loops k-level controllable/observable. We introduce dual points, which utilize the different controllability/observability levels of loops, to make one loop controllable while making another loop observable. We present efficient algorithms to add the minimal hardware possible to make all loops in the data path k-level controllable/observable, without the use of scan FF's. The nonscan DFT techniques were applied to several data path circuits. The experimental results demonstrate the effectiveness of the k-level testability measure, and the use of distributed and dual points, to generate easily testable data paths with reduced hardware overhead. The hardware overhead and the test application time required for the nonscan designs are significantly lower than for the partial scan designs. Most significantly, the experimental results demonstrate the ability of the RT-level DFT techniques to produce nonscan testable data paths, which can be tested at-speed