A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
An exact algorithm for selecting partial scan flip-flops
DAC '94 Proceedings of the 31st annual Design Automation Conference
A Practical Method for Selecting Partial Scan Flip-flops for Large Circuits
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
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For a vast majority of production VLSI designs, the synthesis pipeline is interrupted and technology mapping is performed manually. Here, designers map functional specifications directly onto a more richer set of library blocks that include counters and registers. Typically, these blocks have more than one memory element. The scan version of such a block has all flip-flops chained into a shift register during test mode. For such designs, we show that existing partial scan selection methods may produce sub-optimal solutions. We then propose a new method of selecting scan flip-flops in mapped designs. Our algorithm is based on a new formulation that models the presence of multiple memory elements in a library block and also takes into account both area and performance penalties of scan. We also extend a recently proposed integer linear program (ILP) formulation. A graph transformation that was effective in solving the scan selection problem for large synthesized (or unmapped) designs is shown to be inapplicable for mapped designs. We then develop a new transformation that provably preserves optimum solutions for these mapped designs. Experimental results on three production VLSI circuits having 12,000 to over 50,000 gates are reported.