Test set compaction algorithms for combinational circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Reducing Test Application Time for Full Scan Embedded Cores
FTCS '99 Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing
A Reconfigurable Shared Scan-in Architecture
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
A SmartBIST Variant with Guaranteed Encoding
ATS '01 Proceedings of the 10th Asian Test Symposium
Test Pattern Compression Using Prelude Vectors in Fan-Out Scan Chain with Feedback Architecture
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Hybrid Pattern BIST for Low-Cost Core Testing Using Embedded FPGA Core
IEICE - Transactions on Information and Systems
Survey of Test Vector Compression Techniques
IEEE Design & Test
Low-Cost IP Core Test Using Multiple-Mode Loading Scan Chain and Scan Chain Clusters
DFT '06 Proceedings of the 21st IEEE International Symposium on on Defect and Fault-Tolerance in VLSI Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper proposes a class of test compression for IP (intellectual property) core testing. The proposed compression requires only test cubes for the IP cores and it dose not require the structural information about the IP cores. It uses both a reconfigurable network and classes of coding, namely fixing-flipping coding and fixing-shifting-flipping coding. The proposed compression is evaluated from the viewpoint of compression rates and hardware overhead. For three out of four large ISCAS89 benchmark circuits, the compression rates of the proposed compression are better than those of the four existing test compressions.