Free Kronecker decision diagrams and their application to Atmel 6000 series FPGA mapping

Graph-Based Algorithms for Boolean Function Manipulation

IEEE Transactions on Computers

A new approach to the decomposition of incompletely specified multi-output functions based on graph coloring and local transformations and its application to FPGA mapping

EURO-DAC '92 Proceedings of the conference on European design automation

Efficient representation and manipulation of switching functions based on ordered Kronecker functional decision diagrams

DAC '94 Proceedings of the 31st annual Design Automation Conference

Bottom-up induction of oblivious read-once decision graphs: strengths and limitations

AAAI '94 Proceedings of the twelfth national conference on Artificial intelligence (vol. 1)

Logic Synthesis and Optimization

Logic Synthesis and Optimization

Minimization of Permuted Reed-Muller Trees for Cellular Logic

Selected papers from the Second International Workshop on Field-Programmable Logic and Applications, Field-Programmable Gate Arrays: Architectures and Tools for Rapid Prototyping