Genetic programming: on the programming of computers by means of natural selection
Genetic programming: on the programming of computers by means of natural selection
VHDL for programmable logic
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Genetic programming: an introduction: on the automatic evolution of computer programs and its applications
Principles in the Evolutionary Design of Digital Circuits—Part I
Genetic Programming and Evolvable Machines
A High-Performance, Pipelined, FPGA-Based Genetic Algorithm Machine
Genetic Programming and Evolvable Machines
Register Based Genetic Programming on FPGA Computing Platforms
Proceedings of the European Conference on Genetic Programming
An Extrinsic Function-Level Evolvable Hardware Approach
Proceedings of the European Conference on Genetic Programming
A Pipelined Hardware Implementation of Genetic Programming Using FPGAs and Handel-C
EuroGP '02 Proceedings of the 5th European Conference on Genetic Programming
Pilchard A Reconfigurable Computing Platform with Memory Slot Interface
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Evolving parallel machine programs for a multi-ALU processor
CEC '02 Proceedings of the Evolutionary Computation on 2002. CEC '02. Proceedings of the 2002 Congress - Volume 02
Parallel programs are more evolvable than sequential programs
EuroGP'03 Proceedings of the 6th European conference on Genetic programming
Use of particle swarm optimization to design combinational logic circuits
ICES'03 Proceedings of the 5th international conference on Evolvable systems: from biology to hardware
Promises and challenges of evolvable hardware
IEEE Transactions on Systems, Man, and Cybernetics, Part C: Applications and Reviews
Genetic parallel programming: design and implementation
Evolutionary Computation
Fast genetic programming on GPUs
EuroGP'07 Proceedings of the 10th European conference on Genetic programming
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Genetic Parallel Programming (GPP) is a novel Genetic Programming paradigm. GPP Logic Circuit Synthesizer (GPPLCS) is a combinational logic circuit learning system based on GPP. The GPPLCS comprises a Multi-Logic-Unit Processor (MLP) which is a hardware processor built on a Field Programmable Gate Array (FPGA). The MLP is designed to speed up the evaluation of genetic parallel programs that represent combinational logic circuits. Four combinational logic circuit problems are presented to show the performance of the hardware-assisted GPPLCS. Experimental results show that the hardware MLP speeds up evolutions over 10 times. For difficult problems such as the 6-bit priority selector and the 6-bit comparator, the speedup ratio can be up to 22.