Principles in the Evolutionary Design of Digital Circuits—Part I
Genetic Programming and Evolvable Machines
A Hardware Implementation of a Genetic Programming System Using FPGAs and Handel-C
Genetic Programming and Evolvable Machines
Serial and Parallel Genetic Algorithms as Function Optimizers
Proceedings of the 5th International Conference on Genetic Algorithms
Hardware Evolution at Function Level
PPSN IV Proceedings of the 4th International Conference on Parallel Problem Solving from Nature
Proceedings of the European Conference on Genetic Programming
A Divide-and-Conquer Approach to Evolvable Hardware
ICES '98 Proceedings of the Second International Conference on Evolvable Systems: From Biology to Hardware
Bidirectional Incremental Evolution in Extrinsic Evolvable Hardware
EH '00 Proceedings of the 2nd NASA/DoD workshop on Evolvable Hardware
Design of combinational logic circuits through an evolutionary multiobjective optimization approach
Artificial Intelligence for Engineering Design, Analysis and Manufacturing
Cooperative Coevolution: An Architecture for Evolving Coadapted Subcomponents
Evolutionary Computation
Evolutionary Design of Digital Circuits: Where Are Current Limits?
AHS '06 Proceedings of the first NASA/ESA conference on Adaptive Hardware and Systems
Virtual reconfigurable circuits for real-world applications of evolvable hardware
ICES'03 Proceedings of the 5th international conference on Evolvable systems: from biology to hardware
Evolving multiplier circuits by training set and training vector partitioning
ICES'03 Proceedings of the 5th international conference on Evolvable systems: from biology to hardware
CIS'05 Proceedings of the 2005 international conference on Computational Intelligence and Security - Volume Part I
Promises and challenges of evolvable hardware
IEEE Transactions on Systems, Man, and Cybernetics, Part C: Applications and Reviews
A three-step decomposition method for the evolutionary design of sequential logic circuits
Genetic Programming and Evolvable Machines
Accelerating FPGA-based evolution of wavelet transform filters by optimized task scheduling
Microprocessors & Microsystems
On the Evolution of Hardware Circuits via Reconfigurable Architectures
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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To conquer the scalability issue of evolvable hardware, this paper proposes a multi-virtual reconfigurable circuit (VRC) cores-based evolvable system to evolve combinational logic circuits in parallel. The basic idea behind the proposed scheme is to divide a combinational logic circuit into several subcircuits, and each of them is evolved independently as a subcomponent by its corresponding VRC core. The virtual reconfigurable circuit architecture is designed for implementing real-world applications of evolvable hardware (EHW). in common FPGAs. In our approach, all the VRC cores are realized in a Xilinx Virtex xcv2000E FPGA as an evolvable system to achieve parallel evolution. The proposed method is evaluated on the evolutions of 3-bit multiplier and adder and compared to direct evolution and incremental evolution in the terms of computational effort and hardware implementation cost.