Towards Evolvable IP Cores for FPGAs

  • Authors:
  • Lukáš Sekanina

  • Affiliations:
  • -

  • Venue:
  • EH '03 Proceedings of the 2003 NASA/DoD Conference on Evolvable Hardware
  • Year:
  • 2003

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Abstract

The paper deals with a new approach to the designof adaptive hardware using common Field ProgrammableGate Arrays (FPGA). The ultimate aim is to develop evolvableIP (Intellectual Property) cores. The cores should bereused in the same way as ordinary IP cores are reused. Incontrast to the conventional cores, the evolvable cores areable to perform autonomous evolution of their internal circuits.The cores should be available in the form of HDL source code, i.e. they should be synthesizable into any reconfigurabledevice of a sufficient capacity. The approach is based on implementation of a virtual reconfigurable circuitand a genetic unit in an ordinary FPGA. In the presentedcase study an adaptive image filter is designed, implementedand synthesized. The proposed idea of evolvableIP core could open the way towards defining a businessmodel for evolvable hardware.