Towards the Automatic Design of More Efficient Digital Circuits
EH '00 Proceedings of the 2nd NASA/DoD workshop on Evolvable Hardware
Reducing the number of transistors in digital circuits using gate-level evolutionary design
Proceedings of the 9th annual conference on Genetic and evolutionary computation
Redundancy and computational efficiency in Cartesian genetic programming
IEEE Transactions on Evolutionary Computation
An efficient selection strategy for digital circuit evolution
ICES'10 Proceedings of the 9th international conference on Evolvable systems: from biology to hardware
| Hi-index | 0.00 |
A new method is proposed to minimize the number of gates in combinational circuits using Cartesian Genetic Programming (CGP). We show that when the selection of the parent individual is performed on basis of its functionality solely (neglecting thus the phenotype size) smaller circuits can be evolved even if the number of gates is not considered by a fitness function. This phenomenon is confirmed on the evolutionary design of combinational multipliers.