Principles in the Evolutionary Design of Digital Circuits—Part I
Genetic Programming and Evolvable Machines
Some Aspects of an Evolvable Hardware Approach for Multiple-Valued Combinational Circuit Design
ICES '98 Proceedings of the Second International Conference on Evolvable Systems: From Biology to Hardware
Aspects of Digital Evolution: Geometry and Learning
ICES '98 Proceedings of the Second International Conference on Evolvable Systems: From Biology to Hardware
An Extrinsic Function-Level Evolvable Hardware Approach
Proceedings of the European Conference on Genetic Programming
Proceedings of the European Conference on Genetic Programming
EH '99 Proceedings of the 1st NASA/DOD workshop on Evolvable Hardware
Scalability Problems of Digital Circuit Evolution: Evolvability and Efficient Designs
EH '00 Proceedings of the 2nd NASA/DoD workshop on Evolvable Hardware
Towards the Automatic Design of More Efficient Digital Circuits
EH '00 Proceedings of the 2nd NASA/DoD workshop on Evolvable Hardware
On the practical limits of the evolutionary digital filter design at the gate level
EuroGP'06 Proceedings of the 2006 international conference on Applications of Evolutionary Computing
Evolutionary design of gate-level polymorphic digital circuits
EC'05 Proceedings of the 3rd European conference on Applications of Evolutionary Computing
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Array connectivity is an important feature for measuring the efficiency of evolution. Generally, the connectivity is estimated by array geometry and level-back separately. In this paper, a connectivity model based on the path number between the first node and the last node is esteblished. With the help of multinomial coefficient expansion, a formula for estimating array connectivity is presented. By applying this technique, the array geometry and level-back are taken into account simultaneously. Comparison of connectivity within arrays of different geometries and level-backs becomes possible. Enlightened by this approach, a multi-output node structure is developed. This structure promotes the connectivity without increasing the array size. A multi-objective fitness funciton based on power consumption and critical delay of circuits is proposed, which enables evolved circuits to agree with the requirements of applications. Experimental results show that the proposed approach offers flexibility in constructing circuits and thus improves the efficiency of evolutionary design of circuits.