Genetic programming: on the programming of computers by means of natural selection
Genetic programming: on the programming of computers by means of natural selection
Proceedings of the European Conference on Genetic Programming
Neutrality and the Evolvability of Boolean Function Landscape
EuroGP '01 Proceedings of the 4th European Conference on Genetic Programming
Towards the Automatic Design of More Efficient Digital Circuits
EH '00 Proceedings of the 2nd NASA/DoD workshop on Evolvable Hardware
Prokaryotic Bio-Inspired Model for Embryonics
AHS '09 Proceedings of the 2009 NASA/ESA Conference on Adaptive Hardware and Systems
An efficient selection strategy for digital circuit evolution
ICES'10 Proceedings of the 9th international conference on Evolvable systems: from biology to hardware
Evolving digital circuits using complex building blocks
ICES'10 Proceedings of the 9th international conference on Evolvable systems: from biology to hardware
Evolutionary design of gate-level polymorphic digital circuits
EC'05 Proceedings of the 3rd European conference on Applications of Evolutionary Computing
Redundancy and computational efficiency in Cartesian genetic programming
IEEE Transactions on Evolutionary Computation
The Automatic Acquisition, Evolution and Reuse of Modules in Cartesian Genetic Programming
IEEE Transactions on Evolutionary Computation
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A cell array is a proposed type of custom FPGA, where digital circuits can be formed from interconnected configurable cells. In this paper we have presented a means by which CGP might be adapted to evolve configurations of a proposed cell array. As part of doing so, we have suggested an additional genetic operator that exploits modularity by copying sections of the genome within a solution, and investigated its efficacy. Additionally, we have investigated applying selection pressure for parsimony during functional evolution, rather than in a subsequent stage as proposed in other work. Our results show that solutions to benchmark problems can be evolved with a good degree of efficiency, and that compact solutions can be found with no significant impact on the required number of circuit evaluations.