A graph compaction approach to fault simulation

Authors:
Dov Harel;Balakrishnan Krishnamurthy
Affiliations:
Tektronix Laboratories, Tektronix, Inc., Beaverton, Oregon;Tektronix Laboratories, Tektronix, Inc., Beaverton, Oregon
Venue:
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Year:
1988

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Abstract

We describe a graph compaction based algorithm for fault simulation in combinational circuits. The algorithm consists of reducing the circuit graph by repeatedly removing non-reconvergent vertices. The algorithm have been implemented in Smalltalk and preliminary experimental results are presented. A version of the algorithm outperforms all known fault simulation algorithms on a family of hard circuits.