Test Patterns Compression Technique Based on a Dedicated SAT-Based ATPG

Authors:
Jiri Balcarek;Petr Fiser;Jan Schmidt
Affiliations:
-;-;-
Venue:
DSD '10 Proceedings of the 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools
Year:
2010

Citing 0
Cited 2

Techniques for SAT-based constrained test pattern generation

Microprocessors & Microsystems
SAT-based generation of compressed skewed-load tests for transition delay faults

Microprocessors & Microsystems

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Abstract

In this paper we propose a new method of test patterns compression based on a design of a dedicated SAT-based ATPG (Automatic Test Pattern Generator). This compression method is targeted to systems on chip (SoCs)provided with the P1500 test standard. The RESPIN architecture can be used for test patterns decompression. The main idea is based on finding the best overlap of test patterns during the test generation, unlike other methods, which are based on efficient overlapping of pre-generated test patterns. The proposed algorithm takes advantage of an implicit test representation as SAT problem instances. The results of test patterns compression obtained for standard ISCAS’85 and ‘89benchmark circuits are shown and compared with competitive test compression methods.