Techniques for SAT-based constrained test pattern generation
Microprocessors & Microsystems
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The continuous trend to decrease the cost-per-function and to increase the quality of integrated circuits amplifies the test challenges. Overall low production cost can be achieved only by considering the test area overhead, the test application time and the test quality. The fulfillment of these requirements is possible by application of short tests, use of low-overhead design-for-testability methods/standards and targeting more realistic fault models. The satisfiability-based test pattern generator of compressed skewed-load tests for transition delay faults is proposed. The test application is possible to logic cores of systems-on-chip even with only one storage element per cell in the wrapper boundary register and in the internal scan chain. Therefore, the test area is kept low while the testability of delay faults is ensured. The proposed method represents a new efficient approach for generating compressed skewed-load tests. The experimental results show significant test length reduction and increased fault coverage.