Statecharts: A visual formalism for complex systems
Science of Computer Programming
A protocol test generation procedure
Computer Networks and ISDN Systems
STATEMATE: A Working Environment for the Development of Complex Reactive Systems
IEEE Transactions on Software Engineering
The Multiple Observation Time Test Strategy
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Testable synthesis of high complex control devices
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
FsmTest: functional test generation for sequential circuits
Integration, the VLSI Journal
Synthesis for testability of large complexity controllers
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Protocol Conformance Testing Using Multiple UIO Sequences
Proceedings of the IFIP WG6.1 Ninth International Symposium on Protocol Specification, Testing and Verification IX
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
On the Acceleration of Test Generation Algorithms
IEEE Transactions on Computers
Test generation and verification for highly sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On achieving complete fault coverage for sequential machines
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Sequential test generation and synthesis for testability at the register-transfer and logic levels
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Control-dominated devices are usually modeled as a composition of finite state machines. FSMs can be hierarchically composed to dominate the modeling complexity or can be aggregated into an interacting architecture to partition a complex behavior. A hierarchical or interacting FSM based representation can be extracted from a device's description given by means of a hardware description language. The core of the paper concerns the definition of a complete testing strategy based on the comparison between these FSMs' representations and the structural representations of the device. This comparison simplifies the testing problem by using the functional information to perform scan insertion, redundancies removal and test pattern generation considering the actual stuck-at fault model on the gate-level implementation. Therefore, a fully testable implementation can be thus obtained even for such devices which cannot be satisfactorily analyzed at the gate level.