Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Interconnect design for deep submicron ICs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Partial bus-invert coding for power optimization of application-specific systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Bus encoding to prevent crosstalk delay
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
GLS '97 Proceedings of the 7th Great Lakes Symposium on VLSI
Static Crosstalk-noise Analysis: For Deep Sub-Micron Digital Designs
Static Crosstalk-noise Analysis: For Deep Sub-Micron Digital Designs
Efficient RC low-power bus encoding methods for crosstalk reduction
Integration, the VLSI Journal
Formal derivation of optimal active shielding for low-power on-chip buses
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This research work presents a novel circuit for simultaneous reduction of power, crosstalk and area using bus encoding technique in RC modeled VLSI interconnect. Bus-invert method is used to reduce inter-wire coupling, which is actually responsible for crosstalk, delay and power dissipation in coupled interconnects. The proposed method focuses on simplified and improved encoder circuit for 4, 8 and 16 coupled lines. In past, the researchers developed encoders that usually focused on minimizing power dissipation and/or crosstalk, thereby paying heavy penalty in terms of chip area. However, the proposed encoder and decoder while significantly reducing crosstalk demonstrates an overall reduction of power dissipation by 68.76% through drastically limiting switching activity. Furthermore, while reducing the complexity, chip area and transistor count of the circuit is reduced by more than 57%.