Buffer insertion for noise and delay optimization
DAC '98 Proceedings of the 35th annual Design Automation Conference
Digital systems engineering
Optimal river routing with crosstalk constraints
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Clock distribution using multiple voltages
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Energy efficient high-speed on-chip signaling in deep-submicron CMOS technology
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
Efficient Crosstalk Estimation
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
IEEE Spectrum
Robust Multi-Level Current-Mode On-Chip Interconnect Signaling in the Presence of Process Variations
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Quasi-resonant interconnects: a low power, low latency design methodology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper we propose an efficient technique for energy savings in DSM technology. The core of this method is based on low-voltage signaling over long on-chip interconnect with repeaters insertion to tolerate DSM noise and to achieve an acceptable delay. We elaborate a heuristic algorithm, called VIJIM, for repeaters insertion. VIJIM algorithm has been implemented to design a robust inverter chain for on-chip signaling using 0:25µm, 2.5V,6metal layers CMOS process. An average of 70% of energy-saving has been achieved by reducing the supply voltage from 2.5V down to 1.5V.