Design for Manufacturing in the Semiconductor Industry: The Litho/Design Workshops
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Manufacturing-Aware Physical Design
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
The impact of the nanoscale on computing systems
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Design rule optimization of regular layout for leakage reduction in nanoscale design
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Leakage reduction through optimization of regular layout parameters
Microelectronics Journal
| Hi-index | 0.00 |
In this paper, we briefly describe the lithography developments known as RET (Resolution Enhancement Technologies), which include off-axis illumination in litho tools, Optical and Process Correction (OPC), and phase shifting masks (PSM). All of these techniques are adopted to allow ever smaller features to be reliably manufactured, and are being generally adopted in all manufacturing below 0.25 microns. However, their adoption also places certain restrictions on layouts. We explore these restrictions, and then provide suggestions for layout practices that will facilitate the use of these technologies, especially the generation of a clean target layout for use as input layers for photomask preparation, and the use of verification tools that use process simulation.