Optical proximity correction (OPC): friendly maze routing
Proceedings of the 41st annual Design Automation Conference
RADAR: RET-aware detailed routing using fast lithography simulations
Proceedings of the 42nd annual Design Automation Conference
Maze routing with OPC consideration
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Efficient process-hotspot detection using range pattern matching
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Predictive formulae for OPC with applications to lithography-friendly routing
Proceedings of the 45th annual Design Automation Conference
Neural Network Based Algorithm for Multi-Constrained Shortest Path Problem
ISNN '07 Proceedings of the 4th international symposium on Neural Networks: Advances in Neural Networks
Predicting variability in nanoscale lithography processes
Proceedings of the 46th Annual Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SAT based multi-net rip-up-and-reroute for manufacturing hotspot removal
Proceedings of the Conference on Design, Automation and Test in Europe
High performance lithographic hotspot detection using hierarchically refined machine learning
Proceedings of the 16th Asia and South Pacific Design Automation Conference
DOPPLER: DPL-aware and OPC-friendly gridless detailed routing with mask density balancing
Proceedings of the International Conference on Computer-Aided Design
Simultaneous OPC- and CMP-aware routing based on accurate closed-form modeling
Proceedings of the 2013 ACM international symposium on International symposium on physical design
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In the era of deep sub-wavelength lithography for nanometer VLSI designs, manufacturability and yield issues are critical and need to be addressed during the key physical design implementation stage, in particular detailed routing. However, most existing studies for lithography-friendly routing suffer from either huge run-time due to the intensive lithographic computations involved, or severe loss of quality of results because of the inaccurate predictive models. In this paper, we propose AENEID - a fast, generic and high performance lithography-friendly detailed router for enhanced manufacturability. AENEID combines novel hotspot detection and routing path prediction techniques through modern data learning methods and applies them at the detailed routing stage to drive high fidelity lithography-friendly routing. Compared with existing litho-friendly routing works, AENEID demonstrates 26% to 66% (avg. 50%) of lithography hotspot reduction at the cost of only 18%-38% (avg. 30%) of run-time overhead.