Predicting variability in nanoscale lithography processes

Authors:
Dragoljub Gagi Drmanac;Frank Liu;Li-C. Wang
Affiliations:
University of California, Santa Barbara;IBM, Austin Research Lab;University of California, Santa Barbara
Venue:
Proceedings of the 46th Annual Design Automation Conference
Year:
2009

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Abstract

As lithography process nodes shrink to sub-wavelength levels generating acceptable layout patterns becomes a challenging problem. Traditionally, complex convolution based lithography simulations are used to estimate areas of high variability. These methods are slow and infeasible for large scale full chip analysis. This work proposes a solution to this problem by using machine learning techniques to identify layout areas that are more prone to variability. A novel target layout representation is proposed, and the latest support vector machine (SVM) algorithms are used to detect variability within standard cells and between cells in a simulated full chip layout.