Measuring jitter of high speed data channels using undersampling techniques
ITC '98 Proceedings of the 1998 IEEE International Test Conference
An Automated, Complete, Structural Test Solution for SERDES
ITC '04 Proceedings of the International Test Conference on International Test Conference
Enhanced Resolution Jitter Testing Using Jitter Expansion
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
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This paper presents a time-domain jitter expansion technique for high-speed digital bit sequence jitter testing. While jitter expansion has been applied to phase noise measurements of sinusoidal signals before, its applicability to random clock jitter testing and data-dependent jitter testing have not been explored. The latter problems have wide application and necessitate new analysis procedures given in this paper. Since low phase noise sinusoids can be generated relatively easily as compared to low jitter digital clocks, the proposed technique utilizes a low-frequency sine wave as a reference signal which can be fed to the device under test with less concern for reference signal noise. A special circuit called a jitter-sensor is used for jitter extraction and produces a low-speed output signal with higher jitter values that track the jitter of the high-speed digital test signal. Thus, conventional narrow-bandwidth testers are able to analyze the sensor output. This allows high resolution jitter testing for high-speed digital signals possible at low cost.