Jitter decomposition in ring oscillators
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Jitter Decomposition by Time Lag Correlation
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Experimental evaluation of the jitter generated in timing transfer
IEEE Transactions on Communications
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High performance serial communication systems often require the Bit Error Rate (BER) to be at the level of 10-12 or below. The excessive test time for measuring such a low BER is a major hindrance in testing communication systems cost-effectively. In this paper, we propose a new technique for accurate and efficient estimation of the BER. The proposed technique estimates the BER based on the spectral information of jitter and the characteristics of the clock and data recovery circuit. The method can significantly reduce the production test time for BER testing. Simulation results demonstrate the potential usefulness of the method.