BIST for Phase-Locked Loops in Digital Applications
ITC '99 Proceedings of the 1999 IEEE International Test Conference
A jitter characterization system using a component-invariant vernier delay line
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The paper describes an embedded circuit for the single shot jitter measurement of the clock signal. Based on a jitter amplified technique with a pulse removing mechanism, the picosecond level resolution is achieved in the wide frequency range. In addition, a gain-locked loop calibration scheme is proposed to keep the amplification ratio constant under PVT variations. Fabricated by 0.13-um CMOS process, the tested circuit can achieve a resolution of 2 ps root mean square (rms) jitter at an input range from few tens of megahertz to 1.6 GHz.