High-speed digital design: a handbook of black magic
High-speed digital design: a handbook of black magic
Source-Synchronous Testing of Multilane PCI Express and HyperTransport Buses
IEEE Design & Test
Modular Extension of ATE to 5 Gbps
ITC '04 Proceedings of the International Test Conference on International Test Conference
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The ability to precisely control the timing of digital signals is especially important for multi-GHz testing applications where errors are measured in picoseconds or even 100fs. While many solutions exist for continuous clock-type signals, delay of wide-bandwidth data signals is not so easy. In this paper we introduce a novel technique for adjusting the delay of ~7Gbps data signals on a picosecond scale without significant distortion. The approach is based on a timing/amplitude dependency effect observed in a variable-gain SiGe buffer. A prototype is demonstrated with a variable delay range of about 50ps. This circuit is enhanced by adding a "coarse" delay section, including four 33ps steps, to provide the desired total range of ~140ps. The end application requires several of these circuits for deskewing parallel buses of 6.4Gbps ATE signals. The circuit is also useful for injecting a variable amount of jitter, limited by the fine-delay adjustment range.