Digital systems engineering
Low-string on-chip signaling techniques: effectiveness and robustness
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
On the Realisation of Delay-Insensitive Asynchronous Circuits with CMOS Ternary Logic
ASYNC '97 Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Principles of Asynchronous Circuit Design: A Systems Perspective
Principles of Asynchronous Circuit Design: A Systems Perspective
Bus energy consumption for multilevel signals
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Reconfigurable Blocks Based on Balanced Ternary
Journal of Signal Processing Systems
Design of asynchronous embedded processor with new ternary data encoding scheme
SAMOS'06 Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Arithmetic algorithms for ternary number system
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
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This paper presents a new approach to an on-chip asynchronous transmission system suitable for next generation asynchronous on-chip networks. It implements multivalued logic to reduce the number of wires and a low-voltage swing for lower dynamic power dissipation. Furthermore, the transmission system described here enjoys fully static design and has zero static power consumption. Two versions of the transmitter circuit and the receiver are described. The proposed signaling scheme is compared to a classical dual-rail signaling system with regard to speed, power consumption, and reliability. The simulation results show that the asynchronous ternary logic signaling (ATLS) system delivers over 70% higher bandwidth per wire and consumes over 50% less power than the dual-rail signaling system on 10-mm-long on-chip interconnection.