Digital systems engineering
Point to Point GALS Interconnect
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Interfacing Synchronous and Asynchronous Modules Within a High-Speed Pipeline
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
Automatic Scan Insertion and Test Generation for Asynchronous Circuits
ITC '02 Proceedings of the 2002 IEEE International Test Conference
The VLSI-programming language tangram and its translation into handshake circuits
EURO-DAC '91 Proceedings of the conference on European design automation
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In the coming years, the well-known synchronous design style will not be able to keep pace with the increase speed and capabilities of integration of advanced processes. New design paradigms, like core reuse of the already designed synchronous modules and asynchronous designs, are considered in order to cope with the ever increasing complexity. The future SoCs will contain multiple synchronous and asynchronous cores. Asynchronous design will become more and more common among digital designers, while synchronous-asynchronous interactions will emerge as a key issue in the future SoC designs.This paper will present test strategies for 2-phase asynchronous-synchronous interfaces and vice versa. It will be shown how test vectors can be automatically generated using commercially available ATPG tools. The generated ATPG vectors will be able to test all stuck-at-faults within the asynchronous-synchronous interfaces.