Internal organization of the Alpha 21164, a 300-MHz 64-bit quad-issue CMOS RISC microprocessor
Digital Technical Journal - Special 10th anniversary issue
Simultaneous multithreading: maximizing on-chip parallelism
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
The case for a single-chip multiprocessor
Proceedings of the seventh international conference on Architectural support for programming languages and operating systems
Complexity-effective superscalar processors
Proceedings of the 24th annual international symposium on Computer architecture
The multicluster architecture: reducing cycle time through partitioning
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Digital systems engineering
The Alpha 21264 Microprocessor
IEEE Micro
Multiscalar Execution along a Single Flow of Control
ICPP '97 Proceedings of the international Conference on Parallel Processing
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We propose a separation of the processor units to decrease the communication path lengths. The motivation comes from the increasing importance of intrachip signaling delays. The technique consists in separating the instruction set into types and the die into corresponding units. Every type is able to fully handle data and pointer computations as well as typed address pointers. Hence the processor is composed of very independent machines requiring no inter-machine communications. We show that the fetch path length can be divided by 2 and the data load path length can be decreased of 1/3.