Digital systems engineering
DRAM Circuit Design: A Tutorial
DRAM Circuit Design: A Tutorial
Design of CMOS IO Drivers with Less Sensitivity to Process, Voltage, and Temperature Variations
DELTA '04 Proceedings of the Second IEEE International Workshop on Electronic Design, Test and Applications
Computers and Electrical Engineering
A Novel 1.8 V, 1066 Mbps, DDR2, DFI-Compatible, Memory Interface
ISVLSI '10 Proceedings of the 2010 IEEE Annual Symposium on VLSI
CMOS Circuit Design, Layout, and Simulation
CMOS Circuit Design, Layout, and Simulation
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A 1GHz Double Data Rate 2/3 (DRR2/3) combo Stub Series Terminated Logic (SSTL) driver has been developed for the first time to our knowledge using a 90nm CMOS process. To satisfy the signal integrity requirements the driver strength is dynamically calibrated and the input/output port is efficiently terminated by on-die resistors. Furthermore, the slew-rate can be sufficiently controlled by selecting an appropriate external resistor. The proposed driver design provides all the required output and termination impedances specified by both the DDR2 and DDR3 standards and occupies a small die area of 0.032mm^2 (differential). Experimental results demonstrate its robustness over process, voltage, and temperature variations.