On-chip communication design: roadblocks and avenues
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Technology-based Architectural Analysis of Operand Bypass Networks for Efficient Operand Transport
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 15 - Volume 16
Three-dimensional Integrated Circuit Design
Three-dimensional Integrated Circuit Design
Topology-unaware routing in irregular self-assembled networks-on-chip: an explorative case study
Proceedings of the 2nd international conference on Nano-Networks
Wire cost and communication analysis of self-assembled interconnect models for Networks-on-Chip
Proceedings of the 2nd International Workshop on Network on Chip Architectures
A methodology for constraint-driven synthesis of on-chip communications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An outlook on design technologies for future integrated systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A power-aware mapping approach to map IP cores onto NoCs under bandwidth and latency constraints
ACM Transactions on Architecture and Code Optimization (TACO)
Neural inspired architectures for nanoelectronics
IWANN'07 Proceedings of the 9th international work conference on Artificial neural networks
Leveraging partially faulty links usage for enhancing yield and performance in networks-on-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Bus energy consumption for multilevel signals
IEEE Transactions on Circuits and Systems Part I: Regular Papers
A data capturing method for buses on chip
IEEE Transactions on Circuits and Systems Part I: Regular Papers
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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During the past decade, interconnects have replaced transistors as the dominant determiner of chip performance. To sustain the historical rate of advance in performance, monolithic interconnect technology has rapidly evolved to keep pace withadvances in transistor density and performance. New and radically different interconnect technologies will become increasingly important to future gigascale microsystems.