An Accurate Energy and Thermal Model for Global Signal Buses

Authors:
Krishnan Sundaresan;Nihar R. Mahapatra
Affiliations:
Michigan State University;Michigan State University
Venue:
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Year:
2005

Citing 0
Cited 3

On-Chip Communication Architectures: System on Chip Interconnect

On-Chip Communication Architectures: System on Chip Interconnect
Analysis and simulation of a novel gradually low-K dielectric structure for crosstalk reduction in VLSI

Microelectronics Journal
Bus energy consumption for multilevel signals

IEEE Transactions on Circuits and Systems Part I: Regular Papers

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Abstract

Accurate estimation of energy dissipation and thermal effects in buses is essential to correctly predicting reliability and performance characteristics and packaging requirements of ICs. As fabrication technologies scale down and low-K inter-metal and inter-layer dielectrics are introduced to reduce RC delay, dynamic power dissipation, and crosstalk, study of thermal effects, particularly for global signal buses that switch at high clock frequencies, are becoming more and more important. Further, power dissipation and hence temperature rise and reliability of bus lines are time- and information-dependent, which makes dynamic simulation studies necessary. This paper presents a bus energy dissipation and thermal model that enables designers to simultaneously study energy and thermal effects in global signal buses using real-world address traces. Using this model, the energy dissipation and temperature rise in 32-bit instruction and data address buses are studied with traces obtained from SPEC CPU2000 benchmark programs.