An Integrated Memory Array Processor Architecture for Embedded Image Recognition Systems
Proceedings of the 32nd annual international symposium on Computer Architecture
An Integrated Memory Array Processor for Embedded Image Recognition Systems
IEEE Transactions on Computers
Parallel image understanding on a multi-DSP system
ICCSA'07 Proceedings of the 2007 international conference on Computational science and Its applications - Volume Part II
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High computer performance depends only partially on using faster and more reliable hardware, but to a large extent it depends on the architecture and on the processing techniques. An effective platform that matches general planning strategies is given by the hierarchical paradigm. This is true particularly in the field of image processing and computer vision, which is characterized by very large quantity of sensory data, but in which most of the information collected is meaningless for the task at end. Real time performances can be achieved only by applying some attentional mechanisms that allow to restrict the computation just on the relevant data, at the right time. Several vision systems have been proposed and designed to support the implementation of these strategies. In this work, after introducing a taxonomy of the hierarchical machine vision systems, a short description of the most popular implementations is given.