Optimized mapping for enchancing the operation parallelism in coarse-grained reconfigurable arrays

Authors:
Gregory Dimitroulakos;Michalis D. Galanis;Costas E. Goutis
Affiliations:
VLSI Design Laboratory, Electrical & Computer Eng. Dept., University of Patras, Greece;VLSI Design Laboratory, Electrical & Computer Eng. Dept., University of Patras, Greece;VLSI Design Laboratory, Electrical & Computer Eng. Dept., University of Patras, Greece
Venue:
SMO'06 Proceedings of the 6th WSEAS International Conference on Simulation, Modelling and Optimization
Year:
2006

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Abstract

It is widely known that bandwidth limitations degrade parallel systems' performance. This paper presents a mapping methodology for coarse-grain reconfigurable arrays which alleviates the bandwidth bottleneck by exploiting the processing elements interconnection network for transferring values with data reuse opportunities. A novel mapping algorithm is also proposed that uses a resource-aware modulo scheduling technique. From the application of the proposed mapping approach, significant improvements in performance were achieved while we have also quantified these improvements in respect to crucial architecture parameters such as the memory latency and the register file size. For this reason, our methodology targets on a parametric architecture template which can model a large number of existing architectures of this kind.