Interconnect Power Analysis for a Coarse-Grained Reconfigurable Array Processor

Authors:
Mladen Berekovic;Frank Bouwens;Tom Aa;Diederik Verkest
Affiliations:
Technical University Braunschweig, Braunschweig, Germany 38106;Stichting IMEC Nederland, Eindhoven, The Netherlands 5605 KN;IMEC vzw, DESICS, Leuven, Belgium B-3001;IMEC vzw, DESICS, Leuven, Belgium B-3001
Venue:
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Year:
2009

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Abstract

Coarse-grained reconfigurable array processors (CGRAs) offer a promising path to high performance and power efficient processing. Increasing power dissipation at interconnect wires that comes with advanced process technologies may become a major problem for heavily interconnected CGRA processors. In our study we show that for a typical 90 nm process technology power in wire interconnects is still a fractional part of total power.