Adaptation in natural and artificial systems
Adaptation in natural and artificial systems
Mersenne twister: a 623-dimensionally equidistributed uniform pseudo-random number generator
ACM Transactions on Modeling and Computer Simulation (TOMACS) - Special issue on uniform random number generation
A decade of reconfigurable computing: a visionary retrospective
Proceedings of the conference on Design, automation and test in Europe
Efficient and Accurate Parallel Genetic Algorithms
Efficient and Accurate Parallel Genetic Algorithms
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms in Search, Optimization and Machine Learning
Principles of Computer Architecture
Principles of Computer Architecture
Proceedings of the European Conference on Genetic Programming
A Hardware Genetic Algorithm for the Travelling Salesman Problem on SPLASH 2
FPL '95 Proceedings of the 5th International Workshop on Field-Programmable Logic and Applications
Easily Testable Image Operators: The Class of Circuits Where Evolution Beats Engineers
EH '03 Proceedings of the 2003 NASA/DoD Conference on Evolvable Hardware
Sourcebook of parallel computing
Sourcebook of parallel computing
Circuit Design with VHDL
New Algorithms, Architectures and Applications for Reconfigurable Computing
New Algorithms, Architectures and Applications for Reconfigurable Computing
Reconfigurable Computing: Accelerating Computation with Field-Programmable Gate Arrays
Reconfigurable Computing: Accelerating Computation with Field-Programmable Gate Arrays
A Compact Genetic Algorithm with Elitism and Mutation Applied to Image Recognition
ICIC '08 Proceedings of the 4th international conference on Intelligent Computing: Advanced Intelligent Computing Theories and Applications - with Aspects of Artificial Intelligence
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This work presents a proposal and implementation of a re-configurable parallel architecture, using Genetic Algorithms and applied to synthesis of combinational digital circuits. This reconfigurable parallel architecture uses concepts of computer architecture and parallel processing to obtain a scalable performance. It is developed in VHDL and implemented totally in hardware using FPGA devices. The concept of reconfigurable and parallel architecture enables an easy hardware adaptation to different project requirements. This approach allows applies with flexibility different strategies to synthesis of combinational digital circuits problem.