A reconfigurable arithmetic array for multimedia applications
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
PipeRench: a co/processor for streaming multimedia acceleration
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
Swarm intelligence: from natural to artificial systems
Swarm intelligence: from natural to artificial systems
A decade of reconfigurable computing: a visionary retrospective
Proceedings of the conference on Design, automation and test in Europe
Swarm intelligence
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
Evolution of Parallel Cellular Machines: The Cellular Programming Approach
Evolution of Parallel Cellular Machines: The Cellular Programming Approach
A POEtic architecture for bio-inspired hardware
ICAL 2003 Proceedings of the eighth international conference on Artificial life
The Architecture For A Hardware Immune System
EH '01 Proceedings of the The 3rd NASA/DoD Workshop on Evolvable Hardware
Augmenting a microprocessor with reconfigurable hardware
Augmenting a microprocessor with reconfigurable hardware
Theory of Self-Reproducing Automata
Theory of Self-Reproducing Automata
Self organization on a swarm computing fabric: a new way to look at fault tolerance
Proceedings of the 7th ACM international conference on Computing frontiers
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Parallel implementations are widely used in digital architectures to enhance computational performances, exploiting the number of involved processing units. Cooperative behaviors typical of swarm intelligence can enhance the performances of such systems introducing an amplification effect due to the collective effort of a set of interacting hardware agents. Cooperation can also be exploited like a new weapon to achieve the fault-tolerance goal, with no need for expressly inserted redundant hardware resources. In this paper we present a novel architecture able to address these issues exploiting all the potentiality exposed by this bioinspired approach. A first implementation on CMOS 0.13 µm technology shows the feasibility of such a design style, allowing preliminary simulations and discussions.