Architectural and physical design challenges for one-million gate FPGAs and beyond
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
A decade of reconfigurable computing: a visionary retrospective
Proceedings of the conference on Design, automation and test in Europe
FPGA and CPLD Architectures: A Tutorial
IEEE Design & Test
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In the coming years, the semiconductor industry will face new design challenges due to growing complexity, evolving and diversifying demand and decreasing time-to-market. Re-configurable IC architectures (RAs) add flexibility and decrease silicon-level complexity, but are inefficient in terms of traditional cost functions. Due to increased system-level integration on ICs, the focus will move to system or even end-user conceived performance issues from traditional module-level performance criteria, such as area, power, clock speed, and design efficiency. Other characteristics - dependability, scalability, product-level inter-generation compatibility and effective lifetime - should also be considered. Obviously, traditional cost functions are insufficient to express the full range of design considerations. In this article we outline a methodology for evaluating performance from the user's perspective, analyze various IC architectures using qualitative performance metrics, and present a novel IC architecture, specifically designed to exhibit high qualitative performance.