A hardware/software prototyping environment for dynamically reconfigurable embedded systems
Proceedings of the 6th international workshop on Hardware/software codesign
The Unified Modeling Language user guide
The Unified Modeling Language user guide
Java driven codesign and prototyping of networked embedded systems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
A design flow for partially reconfigurable hardware
ACM Transactions on Embedded Computing Systems (TECS)
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
UML design for dynamically reconfigurable multiprocessor embedded systems
Proceedings of the Conference on Design, Automation and Test in Europe
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Dynamically reconfigurable computing systems (DRCS) provides an intermediate tradeoff between flexibility and performance of computing systems design. Unfortunately, designing DRCS has a highly complex and formidable task. The lack of tools and design flows discourage designers from adopting the reconfigurable computing technology. A UML-based design flow for DRCS is proposed in this article. The proposed design flow is targeted at the execution speedup of functional algorithms in DRCS and at the reduction of the complexity and time-consuming efforts in designing DRCS . In particular, the most notable feature of the proposed design flow is a HW-SW partitioning methodology based on the UML 2.0 sequence diagram, called Dynamic Bitstream Partitioning on Sequence Diagram (DBPSD). To prove the feasibility of the proposed design flow and DBPSD partitioning methodology, an implementation example of DES (Data Encryption Standard) encryption/decryption system is presented in this article.