UML 2.0 Profile for Embedded System Design
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Using UML 2.0 for System Level Design of Real Time SoC Platforms for Stream Processing
RTCSA '05 Proceedings of the 11th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications
Overview of the MPSoC design challenge
Proceedings of the 43rd annual Design Automation Conference
A MDA based SoC Modeling Approach using UML and SystemC
CIT '06 Proceedings of the Sixth IEEE International Conference on Computer and Information Technology
ModES: Embedded Systems Design Methodology and Tools based on MDE
MOMPES '07 Proceedings of the Fourth International Workshop on Model-Based Methodologies for Pervasive and Embedded Software
Designing a Unified Process for Embedded Systems
MOMPES '07 Proceedings of the Fourth International Workshop on Model-Based Methodologies for Pervasive and Embedded Software
Ultra-Fast Downloading of Partial Bitstreams through Ethernet
ARCS '09 Proceedings of the 22nd International Conference on Architecture of Computing Systems
A co-design approach for embedded system modeling and code generation with UML and MARTE
Proceedings of the Conference on Design, Automation and Test in Europe
Synthesized UML, a practical approach to map UML to VHDL
RISE'05 Proceedings of the Second international conference on Rapid Integration of Software Engineering Techniques
UML-Based design flow and partitioning methodology for dynamically reconfigurable computing systems
EUC'05 Proceedings of the 2005 international conference on Embedded and Ubiquitous Computing
Decentralized control for dynamically reconfigurable FPGA systems
Microprocessors & Microsystems
| Hi-index | 0.00 |
In this paper we propose a design methodology to explore partial and dynamic reconfiguration of modern FPGAs. We improve an UML based co-design methodology to allow dynamic properties in embedded systems. Our approach targets MPSoPC (Multiprocessor System on Programmable Chip) which allows area optimization through partial reconfiguration without performance penalty. In our case area reduction is achieved by reconfiguring co-processors connected to embedded processors. Most of the system is automatically generated by means of MDE techniques. Our modeling approach allows designers to target dynamic reconfiguration without being expert of modern FPGAs as many implementation details are hidden during the modeling step. Such a methodology allows design time speedup and a significant reduction of the gap between hardware and software modeling. In order to validate our approach, an object tracking application has been implemented on a reconfigurable system composed of 4 embedded processors and 3 co-processors. Dynamic reconfiguration has been performed for one co-processor which dynamically implements 3 different computations.