A prototype chip of multicontext FPGA with DRAM for virtual hardware
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Wideband CDMA For Third Generation Mobile Communications: Universal Personal Communications
Wideband CDMA For Third Generation Mobile Communications: Universal Personal Communications
A design flow for partially reconfigurable hardware
ACM Transactions on Embedded Computing Systems (TECS)
Novel Switch Block Architecture Using Non-Volatile Functional Pass-Gate for Multi-Context FPGAs
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
A cost-effective context memory structure for dynamically reconfigurable processors
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
| Hi-index | 0.00 |
Dynamic reconfiguration on fine-grained architecture can only be reached by multi-context FPGAs when reconfiguration time is a critical issue. Unfortunately the multiple contexts bring power and area overhead. This paper introduces the Dynamic Unifier and reConfigurable blocK (DUCK), a new structure to perform efficiently dynamic reconfiguration. The DUCK allows to separate the configuration path and the configuration registers which facilitates simultaneous configuration and computing steps. The reconfiguration process using the DUCK concept is presented in detail and synthesis results are given for different structures. Our solution is finally validated with the implementation of a WCDMA receiver on a multi-context embedded FPGA and demonstrates the interest and the efficiency of using dynamic reconfiguration.