A case for redundant arrays of inexpensive disks (RAID)
SIGMOD '88 Proceedings of the 1988 ACM SIGMOD international conference on Management of data
High-speed switch scheduling for local-area networks
ACM Transactions on Computer Systems (TOCS)
A New Routing Algorithm for a Class of Rearrangeable Networks
IEEE Transactions on Computers
On the Correctness of Inside-Out Routing Algorithm
IEEE Transactions on Computers
The iSLIP scheduling algorithm for input-queued switches
IEEE/ACM Transactions on Networking (TON)
Work-Efficient Routing Algorithms for Rearrangeable Symmetrical Networks
IEEE Transactions on Parallel and Distributed Systems
Fair Scheduling in Internet Routers
IEEE Transactions on Computers
Rearrangeability of $(2\protectn-1)$-Stage Shuffle-Exchange Networks
SIAM Journal on Computing
Analysis of the parallel packet switch architecture
IEEE/ACM Transactions on Networking (TON)
Banyan networks for partitioning multiprocessor systems
ISCA '73 Proceedings of the 1st annual symposium on Computer architecture
Computer Architecture: A Quantitative Approach
Computer Architecture: A Quantitative Approach
Multistage-Based Switching Fabrics for Scalable Routers
IEEE Transactions on Parallel and Distributed Systems
Parallel Algorithms to Set Up the Benes Permutation Network
IEEE Transactions on Computers
On the Rearrangeability of 2(Iog2N) -1 Stage Permutation Networks
IEEE Transactions on Computers
The Universality of the Shuffle-Exchange Network
IEEE Transactions on Computers
The Indirect Binary n-Cube Microprocessor Array
IEEE Transactions on Computers
On a Class of Multistage Interconnection Networks
IEEE Transactions on Computers
Performance of Processor-Memory Interconnections for Multiprocessors
IEEE Transactions on Computers
Access and Alignment of Data in an Array Processor
IEEE Transactions on Computers
The Performance of Multistage Interconnection Networks for Multiprocessors
IEEE Transactions on Computers
Matching output queueing with a combined input/output-queued switch
IEEE Journal on Selected Areas in Communications
Journal of Systems and Software
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Scalable high performance routers and switches are required to provide a larger number of ports, higher throughput, and good reliability. Most of today’s routers and switches are implemented using single crossbar as the switched fabric. The single crossbar complexity increases at O(N2) in terms of crosspoint number, which might become unacceptable for scalability as the port number (N) increases. A delta class self-routing multistage interconnection network (MIN) with the complexity of O(N 脳 log2N) has been widely used in the ATM switches. However, the reduction of the crosspoint number results in considerable internal blocking. A number of scalable methods have been proposed to solve this problem. One of them uses more stages with recirculation architecture to reroute the deflected packets, which greatly increase the latency. In this paper, we propose an interleaved multistage switching fabrics architecture and assess its throughput with an analytical model and simulations. We compare this novel scheme with some previous parallel architectures and show its benefits. From extensive simulations under different traffic patterns and fault models, our interleaved architecture achieves better performance than its counterpart of single panel fabric. Our interleaved scheme achieves speedups (over the single panel fabric) of 3.4 and 2.25 under uniform and hot-spot traffic patterns, respectively at maximum load (p=1). Moreover, the interleaved fabrics show great tolerance against internal hardware failures.