Performance of buffered multistage interconnection networks in a nonuniform traffic environment
Journal of Parallel and Distributed Computing
Generating systems of equations for performance evaluation of multistage interconnection networks
Journal of Parallel and Distributed Computing
Analysis and Simulation of Buffered Delta Networks
IEEE Transactions on Computers
Performance of Processor-Memory Interconnections for Multiprocessors
IEEE Transactions on Computers
Fault tolerant irregular augmented shuffle network
CEA'07 Proceedings of the 2007 annual Conference on International Conference on Computer Engineering and Applications
Comparative study of blocking mechanisms for packet switched Omega networks
EHAC'07 Proceedings of the 6th WSEAS International Conference on Electronics, Hardware, Wireless and Optical Communications
An Analytical Performance Model for Multistage Interconnection Networks with Blocking
CNSR '08 Proceedings of the Communication Networks and Services Research Conference
International Journal of Communication Systems
Design and implementation of Multistage Interconnection Networks using Quantum-dot Cellular Automata
Microelectronics Journal
International Journal of Network Management
Performance Analysis of a Packet Switch Based on Single-Buffered Banyan Network
IEEE Journal on Selected Areas in Communications
Journal of Network and Computer Applications
Hi-index | 0.00 |
Multistage interconnection networks (MINs) are a basic class of switch-based network architectures, which are used for constructing scalable parallel computers or for connecting networks. Semi-layer MINs are a special case of MINs. A performance evaluation of semi-layer MINs (using simulation models) is presented in this paper. The configurations of the under study networks apply a conflict drop resolution mechanism. The proposed architecture's performance is studied under uniform traffic conditions and various offered loads, buffer-lengths and MIN sizes. In this paper, the improvements on semi-layer MIN performance, in terms of throughput and latency, are demonstrated quantitatively. These performance measures can be valuable tools for designers of parallel multiprocessor systems and networks, in order to minimize the overall deployment costs and help deliver efficient systems.