Fault tolerant irregular augmented shuffle network

  • Authors:
  • Harsh Sadawarti;P. K. Bansal

  • Affiliations:
  • Deptt. of Computer Science & Engg., RIMT-Institute of Engineering & Technology, Mandi Gobindgarh, Punjab, India;GZCET, Bathinda, Punjab, India

  • Venue:
  • CEA'07 Proceedings of the 2007 annual Conference on International Conference on Computer Engineering and Applications
  • Year:
  • 2007

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Abstract

The Performance of a system depends directly on the time required to perform an operation and number of these operations that can be performed concurrently. High performance computing systems can be designed using parallel processing. The effectiveness of these parallel systems rests primarily on the communication network linking processors and memory modules. Hence, an interconnection network that provides the desired connectivity and performance at minimum cost is required for communication in parallel processing systems. Multistage interconection networks provide a compromise between shared bus and crossbar networks. In this paper, a new class of Irregular, Fault-tolerant multistage interconnection network named as Irregular Augmented Shuffle Network (IASN) has been proposed. The network has less number of stages as compared to existing irregular networks. Various performance parameters have been analyzed which shows better performance of the proposed network than the existing networks. The reliability of a network is evaluated in terms of MTTF. It has been the IASN has a higher MTTF for upper and lower bound in comparison bound in comparison to networks such as ASEN-2 and ABN and is comparable to FT network.