The Performance of the Cedar Multistage Switching Network
IEEE Transactions on Parallel and Distributed Systems
Hierarchical multistage interconnection network for shared-memory multiprocessor system
SAC '97 Proceedings of the 1997 ACM symposium on Applied computing
Analysis of shared buffer switches under non-uniform traffic pattern and global flow control
Computer Networks: The International Journal of Computer and Telecommunications Networking
Generating systems of equations for performance evaluation of multistage interconnection networks
Journal of Parallel and Distributed Computing
Performance Analysis of Finite Buffered Multistage Interconnection Networks
IEEE Transactions on Computers
Switch fabric architecture analysis for a scalable bi-directionally reconfigurable IP router
Journal of Systems Architecture: the EUROMICRO Journal
Performance Analysis of dual priority single-buffered blocking Multistage Interconnection Networks
ICNS '07 Proceedings of the Third International Conference on Networking and Services
An Analytical Performance Model for Multistage Interconnection Networks with Blocking
CNSR '08 Proceedings of the Communication Networks and Services Research Conference
Routing and Performance Evaluation of Dual Priority Delta Networks under Hotspot Environment
AFIN '09 Proceedings of the 2009 First International Conference on Advances in Future Internet
Review: Performance estimation of banyan semi layer networks with drop resolution mechanism
Journal of Network and Computer Applications
Performance Analysis of a Packet Switch Based on Single-Buffered Banyan Network
IEEE Journal on Selected Areas in Communications
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In this paper, we model, analyze and evaluate the performance of a 2-class priority architecture for finite-buffered multistage interconnection networks (MINs). The MIN operation modelling is based on a state diagram, which includes the possible MIN states, transitions and conditions under which each transition occurs. Equations expressing state and transition probabilities are subsequently given, providing a formal model for evaluating the MIN's performance. The proposed architecture's performance is subsequently analyzed using simulations; operational parameters, including buffer length, MIN size, offered load and ratios of high priority packets which are varied across experiments to gain insight on how each parameter affects the overall MIN performance. The 2-class priority MIN performance is compared against the performance of single priority MINs, detailing the performance gains and losses for packets of different priorities. Performance is assessed by means of the two most commonly used factors, namely packet throughput and packet delay, while a performance indicator combining both individual factors is introduced, computed and discussed. The findings of this study can be used by network and interconnection system designers in order to deliver efficient systems while minimizing the overall cost. The performance evaluation model can also be applied to other network types, providing the necessary data for network designers to select optimal values for network operation parameters.