A Simulation Study of the CRAY X-MP Memory System
IEEE Transactions on Computers
Exploring and exploiting wire-level pipelining in emerging technologies
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Creating a World of Smart Re-configurable Devices
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Processor-memory interconnections for multiprocessors
ISCA '79 Proceedings of the 6th annual symposium on Computer architecture
Quantum-Dot Cellular Automata Design Guideline
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Performance of Processor-Memory Interconnections for Multiprocessors
IEEE Transactions on Computers
Access and Alignment of Data in an Array Processor
IEEE Transactions on Computers
Design and simulation of modular 2n to 1 quantum-dot cellular automata (QCA) multiplexers
International Journal of Circuit Theory and Applications
A new quantum-dot cellular automata full-adder
Microelectronics Journal
Design and Evaluating Carbon Nanotube Interconnects for a Generic Delta MIN
PDP '11 Proceedings of the 2011 19th International Euromicro Conference on Parallel, Distributed and Network-Based Processing
QCADesigner: a rapid design and Simulation tool for quantum-dot cellular automata
IEEE Transactions on Nanotechnology
Implementation of a crossbar network using quantum-dot cellular automata
IEEE Transactions on Nanotechnology
A comparative analysis and design of quantum-dot cellular automata memory cell architecture
International Journal of Circuit Theory and Applications
Review: Performance estimation of banyan semi layer networks with drop resolution mechanism
Journal of Network and Computer Applications
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Quantum-dot Cellular Automata (QCA) is a promising nanotechnology with ultra-small feature size and ultra-low power consumption compared with transistor-based technologies. During the past decade the QCA has been carefully studied, and it has demonstrated the ability of using quantum phenomena for implementing logical devices. Multistage Interconnection Networks (MINs) have been frequently suggested as the connection means in parallel systems. This architecture provides the maximum bandwidth to the components, and the minimum latency access to memory modules. They are generally accepted concepts in the semiconductor industry for solving problems related to on-chip communications. Although there have been a large amount of researches on MINs for parallel processing, there seems to be surprising attempts to utilize the unique characteristics of QCA for designing and implementing of MINs. In an effort to fill this gap, this paper presents the first design methodology of MINs using QCA. To demonstrate the functionality and validity of the proposed methodology, performance evaluations of MINs using QCADesigner simulator are given and analyzed.